1. Field of the Invention
The present invention relates to a control circuit of power supply unit, a power supply unit and control method thereof, more particularly to a control circuit of power supply unit in which the voltage value of outputted voltage is controlled corresponding to an instruction from outside, a power supply unit and control method thereof.
2. Description of Related Art
In technical field of semiconductor device, reduction of the voltage of a power supply unit has been accelerated with intensified processing velocity and integration. However, it is considered that the voltage of the power supply unit demanded in each semiconductor device varies depending on a difference of development of manufacturing technology. When an interface is assured between different semiconductor devices in a system apparatus constituted of a combination of plural semiconductor devices, the voltage amplitude of I/O signals sometimes may be different. As an art for assuring an interface between the semiconductor devices having a different power supply voltage, the art exemplified in Japanese Unexamined Patent Publication No. 2002-111470 has been proposed.
FIG. 7 shows an example. A case of interfacing a control LSI 100 such as ASIC with a dynamic memory (hereinafter referred to as DDR memory) 200 which exerts DDR function is considered. For example, assume that the DDR memory 200 is actuated at power supply voltage Vdd2 of 2.5 V and 1.25 V which is half of the power supply voltage Vdd2 is set to the interface circuit as terminal voltage VTT. Contrary to this, assume that the control LSI 100 is actuated at a power supply voltage Vdd of 1.2 V.
In the DDR memory 200 having a high velocity interface circuit, the voltage amplitude width is limited to ±200 mV around the terminal voltage VTT (for example, 1.25 V) in order to suppress propagation delay of the signal. The maximum value of the interface signal is 1.45 V which is the terminal voltage VTT (1.25 V)+200 mV and this value exceeds 1.2 V, which is the power supply voltage Vdd of the control LSI 100.
Then, the low level side voltage of the control LSI 100 is set to a voltage raised relative to the ground to match the terminal voltage VTT (1.25 V) with the voltage of ½ the power supply voltage Vdd of the control LSI 100. That is, the low level side voltage of the control LSI 100 is set to 0.65 V and correspondingly, the power supply voltage is set to 1.85 V (=1.2 V+0.65 V). The interface signal vibrates in amplitude of 1.25 V±200 mV, so that the voltage amplitude width of the interface signal settles within the operating voltage range of the control LSI 100 thereby enabling direct interfacing with the DDR memory 200.
The electric characteristic and other physical properties of devices such as MOS transistor constituting the semiconductor device come likely to be affected by dispersion of production quality because of miniaturization of the semiconductor device accompanying the intensified processing velocity and integration, thereby sometimes leading to increase in the dispersion of production quality among individual semiconductor devices. It has been known that the electric characteristic and other physical properties of various devices change due to a difference in usage environment such as ambient temperature. Such changes in characteristic sometimes appear more conceivably due to influences of reduction in voltage for use and it is considered that sufficient characteristics cannot be secured under every usage environment.
While the reduction in voltage for use in the semiconductor device accompanying the miniaturization has been accelerated due to demand for intensification of operating velocity, it is necessary to suppress the threshold voltage to a low voltage in order to operate the MOS transistor at high velocity. However, the MOS transistor having a low threshold voltage can have such a characteristic that consumption current increases due to a leak current penetrating between its source and drain when it is not conductive. To reduce this leak current, it is considered to deepen the threshold voltage by applying a voltage bias to the back gate for the MOS transistor to exert back gate bias effect. That is, it comes that the low threshold voltage necessary for securing a characteristic of high speed operation conflicts with a high threshold voltage necessary for securing a characteristic of low consumption current.
Thus, when the semiconductor device is stopped, voltage bias of increasing the back gate bias effect is carried out to deepen the threshold voltage of the MOS transistor thereby reducing the current consumption by leak current as disclosed in Japanese Unexamined Patent Publication No. H7(1995)-176624. At operation time, the high-velocity operation is met by executing the voltage bias of reducing the back gate bias effect to shallow the threshold voltage of the MOS transistor. This is technology for satisfying both a high velocity response at the operation time and the low consumption current at standby time in the semiconductor device by dynamically controlling the voltage bias to the back gate of the MOS transistor.